Advances in integration technology have led to the development of a three dimensionally stacked LSI approach taken in favor of the conventional two-dimensional LSI approach. Some types of three dimensional integration include package stacking, die stacking, and wafer stacking. Among the wafer stacking approach, a technique called Through-Silicon-Via (TSV) can be used to extend a via hole through a substrate so that a conductive via may be formed that completely penetrates the substrate. In turn, multiple substrates including TSVs can be stacked on one another to achieve three dimensional integration. In particular, the TSVs of different substrates can conduct signals from one substrate to another without the use of, for example, wires.
Two approaches that can be used in the formation of TSVs include a “via first” approach and a “via last” approach. According to a via first approach, TSVs are formed through the substrate before a back end of line process, for example, a metal interconnection process, is accomplished. Furthermore, the via first approach may be used before CMOS devices are formed in the substrates. According to the via first approach, vias can be formed in the substrates to only partially penetrate the substrate wherein after the CMOS and back end of line processing can be provided. Subsequently, the substrates can be thinned so that the vias are exposed and bound together to achieve a three-dimensional stacked structure.
Alternatively, the TSVs can be formed after the formation of the CMOS devices but before the back end of line processing. In particular, the CMOS devices can be formed on the substrate whereupon the vias can be formed to partially penetrate the substrate. Then, the back end of line processing can be provided and followed by a thinning process to complete the TSVs. Finally, the substrates having the TSVs formed therein can be bonded together to provide the three dimensionally stacked structure.
According to the via first approach, vias can be formed in the substrate either before the CMOS devices are formed or before the back end of line processing is provided. For example, the vias can be formed before the formation of CMOS devices by first forming vias that partially penetrate the substrate. Then, the C-MOS and back end of line processing can be provided and followed by a thinning process, which can complete the formation of the TSVs and the substrate. Subsequently, multiple substrates including the TSVs can be bonded together to provide the three dimensionally stacked structure.
According to the via last approach, the vias can be formed during or after the back end of line processing (BEOL) or after a bonding process. When the TSVs are formed during the BEOL, the process can be referred to as a “TSV middle process.” Conventionally, the TSV middle process can be included in the TSV last process as well. For example, processes for the formation of layer in a CMOS process, such formation of ILD, metal 1 TSV, and metal 2 processes.) For example, the via last approach can be used to provide TSVs after the back end of line processing, but before bonding by forming CMOS devices and a back end of line processing before the formation of vias which partially penetrate the substrate. Subsequently, a thinning process can be used to complete the TSV structure, which penetrates the substrate whereupon a bonding process can be used to connect the substrates including the TSV structures to provide the three dimensionally stacked structure.
Alternatively, the via last approach can be used to provide the TSVs after the bonding. For example, the CMOS and back end of line processing can be provided and followed by the bonding of separate wafers together. The bonding wafers can then be thinned to form the TSVs to provide the three dimensionally stacked structure.
TSV structures are also discussed in, for example, the following U.S. patent documents: U.S. Pat. Nos. 6,916,725, 7,214,615, 7,282,444, and U.S. Patent Publication No. 2004/0245623.